Class-D Digital Audio Amplifier Evaluation Board

General Description

The RT9120S is a high efficiency, I²S-input, stereo channel audio power amplifier delivering maximum 2x30W into 8Ω BTL speaker loads. It can deliver over 94% power efficiency at 2x10W and eliminate the need for heatsink. The built-in anti-pop functions can reduce the speaker’s pop noise under all kind of scenarios. Built-in protection circuits can provide over-temperature, over-current, over-voltage, under-voltage protections and report error status. The RT9120S is a 3-wired device receiving all clocks from external sources with standard I²S, Left-justified, Right-justified or TDM formats. It can support wide input sampling rate from 8kHz to 192kHz. The RT9120S features one band DRC and flexible input mixer, and power clipping.

Performance Specification Summary

Summary of the RT9120S Evaluation Board performance specificiaiton is provided in Table 1. PVDDL = PVDDR = AVCC = 12V, DVDD = 3.3V, RL = 8Ω, TA = 25C, f_SW = 384KHz, L = 10µH, C = 0.47µF, unless otherwise specified.

Table 1. RT9120S Evaluation Board Performance Specification Summary

Note: Measurements were made using the RT9120S_EVM board and Audio Precision System 2722 with AUX-0025 low-pass filter.

Operations

1. Connect input power supply (4.5V < PVDD < 26.4V) and ground to PDD and GND pins respectively.

2. Connect input power supply (3.3V) and ground to DVDD and GND pins respectively.

3. The 2X5 Header I²S source input to JP2 (PIN4 = LRCK, PIN6 = SCLK, PIN8 = SDI, PIN10 = SDO).

4. The 2X3 Header I²C source input to J2 (PIN1 = PVSS, PIN3 = SCL, PIN5 = SDA).

5. The 1X3 Header (JP7) is the PWDNB. (JP7, Short PIN1;2 = Disable, Short PIN2;3 = Enable).

6. The 1X3 Header (JP11) is the MUTE_N. (JP11, Short PIN1;2 = Disable, Short PIN2;3 = Enable).

7. The 1X3 Header (JP8) is the FAULTB.

8. The 1X3 Header (JP9, JP25) is the A_SEL. (JP9 is for the 600kΩ use, Short PIN1;2 = 1A, Short PIN2;3 = 1B, JP25 is for the 0Ω use, Short PIN1;2 = 18, Short PIN2;3 = 19 ). See Table 2.

9. The R24/R25 0Ω connect in series is PBTL-mode.

10. Connect speaker to the GP5 (OUT_PL),GP6 (OUT_NL),GP7 (OUT_NR), GP8 (OUT_PR).

Table 2. A_SEL Setting

Detailed Description of Hardware

Headers Description and Placement

Carefully inspect all the components used in the EVB according to the following Bill of Materials table, and then make sure all the components are undamaged and correctly installed. If there is any missing or damaged component, which may occur during transportation, please contact our distributors or e-mail us at evb_service@richtek.com.

Test Points

The EVB is provided with the test points and pin names listed in the table below.

Bill of Materials

Typical Applications

EVB Schematic Diagram

Measure Result

PWM = 384kHz

Evaluation Board Layout

Figure 1. Top View (1^st layer)

Figure 2. PCB Layout—Inner Side (2^nd Layer)

Figure 3. PCB Layout—Inner Side (3^rd Layer)

Figure 4. Bottom View (4^th Layer)